Measured result · PCB routing benchmark
1UA-AGE reaches full routing-completion parity on two PCB benchmarks
1UA-AGE reached 100% routing completion on both public benchmark classes: STRF at 98/98 in three final runs, and STM32 at 211/211 in three final runs. DeepPCB publishes 98/98 and 210/210 respectively. This is full parity against the completion evidence the competitor publishes—not a claim about undisclosed infrastructure, runtime, identical topology or manufacturing readiness.
Full routing-completion parity · two benchmarks · six final runs
Frozen input
Counted result
Four inspectable views of the routed board
What was held constant
- The same frozen STRF fixture was used for all three final runs; nothing was pre-routed.
- The public before and after images use the same KiCad 10.0.5 viewport, scale, orientation, layer set and zone-outline mode.
- The three runs produced different routing solutions, then passed the same run-local acceptance procedure.
Three final runs, one result
464 tracks · 18 vias · 339.8 mm
459 tracks · 18 vias · 339.7 mm
298 tracks · 19 vias · 373.9 mm
Each run introduced 0 new routing-induced DRC violations. This is not a DRC-clean claim: run C1 retains 195 baseline violations, down from 295 in the bare fixture.
Like-for-like public comparison
DeepPCB publishes completed routing results for two boards. 1UA-AGE reached the same published outcome—100% routing completion—on both benchmark classes, with three final accepted runs per board. The disclosed evidence supports this statement:
Full parity was achieved on the competitor’s published completion criterion: STRF 100% ↔ 100%, STM32 100% ↔ 100%.
Why 210/210 and 211/211 are still completion parity
Both are 100% completion results for the same STM32 benchmark class in their respective declared representations. DeepPCB publishes 210/210 in its Altium representation; the pinned 1UA-AGE KiCad conversion contains 211 obligations and completed 211/211 in T1, T2 and T3, with 19/19 applicable gates and 0 new routing-induced DRC violations each time. The one-item denominator difference is a CAD-conversion and verifier-semantics difference—not an extra connection completed by 1UA-AGE. It prevents an object-by-object equality claim, but it does not negate parity on the completion evidence DeepPCB publishes. 1UA-AGE did not use Altium Designer.
Independent visual review
Serhii Kondratiev, PhD, Senior Lecturer at Odesa Polytechnic, completed an independent visual engineering review of the supplied PCB files and positively assessed the visible placement and routing. The review was visual; it was not an electrical, fabrication or physical validation.
Read the independent review →Claim boundaries
- No runtime comparison: the two published time measurements cover different scopes.
- No claim of fewer vias, better topology, DRC cleanliness or general superiority.
- No infrastructure comparison: DeepPCB does not publish a comparable hardware and execution-infrastructure record on these benchmark pages.
- Not electrically verified, not physically validated and not manufacturing-ready.
- The canonical runs have not been independently reproduced.
Primary public sources
DeepPCB · STRF benchmark ↗DeepPCB · STM32 benchmark ↗1UA-AGE Proof and Disclosure Policy →“Models propose. Engineering tools verify.”
Evgeniy Vasyliev, Founder, 1UA-AGE
Comparable media assets
Download the same before and after views used above. They preserve the measured board view and stated claim boundaries.