Independent review · PCB benchmark
Independent engineering expert reviews 1UA-AGE PCB benchmark layouts
Independent visual engineering review completed
Serhii Kondratiev, PhD, Senior Lecturer, Department of Information Systems at Odesa Polytechnic National University and an engineer in radio communication and broadcasting, has completed an independent visual review of PCB layouts produced during the 1UA-AGE benchmark campaign.
The review assessed the component placement and routing visible in the supplied STRF and STM32 board files. The assessment was positive, with explicit limits on what a visual review can establish.
Kondratiev assessed the overall placement and routing quality positively and described the result as a substantial advance over the conventional autorouting tools used in his own engineering practice. In his written response, he concluded (translated from Russian):
“Overall, the board routing and component placement are at a high level and can save 90–95% of an engineer’s work, sharply reducing labour costs.”
Serhii Kondratiev, PhD
The 90–95% figure is Serhii Kondratiev’s professional estimate based on his visual review and engineering experience. It is not a measured KPI, a controlled productivity experiment or a guaranteed commercial cost reduction by 1UA-AGE.
This was a visual layout review. It was not an electrical-design verification, manufacturing release, certification or physical validation.
What was reviewed
- Overall component placement
- Routing quality and board organisation
- Visible unfinished connections
- Whether the supplied files were sufficient to support broader engineering claims
The reviewer examined the PCB artifacts supplied by 1UA-AGE in read-only form. The review was conducted independently from the development process: the reviewer did not modify the boards or participate in producing the benchmark results.
What the review found
The visual assessment of component placement and routing was positive.
The review also identified an unresolved reset connection in a viewed earlier STRF revision. Kondratiev stressed that if an AI system does not report such an unfinished connection as an error, subsequent human verification is mandatory.
According to information provided to the reviewer, the issue was corrected in later board versions. The supplied package did not provide a sufficiently clear canonical-revision map or an immediately accessible authoritative schematic, so the observed issue could not be unambiguously bound to the later canonical STRF artifact solely from the files viewed during the review.
An unfinished mandatory net blocks a claim that the specific reviewed board revision is fully routed and prevents its release for manufacturing. It does not, by itself, establish the state of a different or later revision.
Relationship to the benchmark results
After the extended development and debugging campaign, 1UA-AGE recorded the following internal results in a pinned KiCad environment:
DeepPCB published 98/98 in KiCad
19/19 applicable acceptance checks · zero new routing-induced DRC violations
DeepPCB has published 98/98 for STRF in KiCad and 210/210 for STM32 in Altium. Because the source CAD representations, tools and acceptance denominators differ, 211/211 does not mean superiority over 210/210. 1UA-AGE makes no normalised claim about speed, via count, topology or layout quality.
The later canonical 1UA-AGE results were not independently reproduced or electrically verified as part of this visual review. They remain internally reproducible, scope-bounded software-tool results.
What this review proves — and what it does not
The review provides independent supporting evidence that the examined layouts exhibit strong visible placement and routing quality. It also demonstrates why a technically promising board and a sufficient evidence package are separate requirements.
- Electrical correctness
- Manufacturing readiness
- Physical functionality
- Full end-to-end autonomous mission completion
- Universal engineering competence
- Superiority over DeepPCB or another system
Next steps
The public benchmark record now presents comparable before-and-after board views and binds each measured claim to its stated acceptance scope. Detailed engineering evidence remains controlled rather than being published as an archive. Independent reproduction of the canonical runs, electrical review, manufacturer assessment, fabrication and physical testing remain the next verification stages.
Public sources
DeepPCB public benchmark page ↗1UA-AGE Proof and Disclosure Policy →1UA-AGE is a Ukrainian deep-tech project building an evidence-governed Artificial General Engineer for the physical world.
Models propose. Engineering tools verify.